The rapid evolution of artificial intelligence demands a fundamental shift in how we design and manufacture semiconductor chips. Traditional sequential development methods are no longer sufficient to meet the dual challenges of soaring performance requirements and energy efficiency. This Q&A explores the key challenges and innovations that are reshaping chipmaking in the AI era, drawing parallels from large-scale scientific projects like the Human Genome Project.

Why does AI chipmaking need a new operating paradigm?

Historical breakthroughs, such as the Human Genome Project, succeeded because they moved beyond individual brilliance to a collaborative model: concentrating global talent around a single mission, sharing platforms and infrastructure, and collapsing feedback loops. The AI era presents a similar engineering race. Every company is striving to deliver higher-performing AI systems faster. However, performance is no longer solely about compute speed. Data movement now dominates AI workloads—moving bits often consumes as much or more energy than computation itself. Sequential, siloed innovation cannot keep pace when timelines are compressed and stakes are high. A new paradigm is required that integrates expertise across disciplines, accelerates iteration cycles, and tackles system-level challenges from the start.

What are the three key domains for energy-efficient AI?

The path to energy-efficient AI runs through system-level engineering that spans three tightly interconnected domains: Logic, where performance per watt depends on efficient transistor switching, low-loss power delivery, and signal integrity through dense wiring stacks. Memory, where surging bandwidth and capacity demands expose the memory wall—processor capability advances faster than memory access speeds. Advanced packaging, where 3D integration, chiplet architectures, and high-density interconnects bring compute and memory closer together, enabling system designs that monolithic scaling can no longer sustain. These three domains must be optimized together because gains in one are limited by constraints in the others.

How does data movement impact AI system performance and energy?

In many AI workloads, moving data (bits) consumes as much or more energy than the actual compute operations. This is because the energy cost of transporting data across chips, between memory and processor, and through interconnects is significant. Reducing the energy required per bit of data moved can extend system-level performance alongside gains in peak compute. Therefore, innovations that shorten the distance data travels—such as 3D integration or chiplet architectures—or that increase the efficiency of interconnects are crucial. Addressing the data movement problem is not just about faster memory; it requires holistic optimization across logic, memory, and packaging to minimize energy waste and improve overall system efficiency for AI.

Why can't the three domains be optimized independently?

These domains—logic, memory, and advanced packaging—are tightly coupled. Gains in logic efficiency stall without sufficient memory bandwidth to feed data to the processors. Advances in memory bandwidth fall short if packaging cannot deliver physical proximity within thermal and mechanical constraints. Conversely, packaging innovations are constrained by the precision of front-end device fabrication and back-end integration processes. In the angstrom era, the hardest problems arise at the boundaries between these domains: between compute and memory in the package, between front-end and back-end integration, and between the tightly coupled process steps needed for precise 3D fabrication. Optimizing in isolation leads to bottlenecks; only concurrent engineering can unlock the full performance and energy efficiency potential.

How does the traditional R&D model fall short in the angstrom era?

For decades, semiconductor R&D followed a relay race model: capabilities developed in one part of the ecosystem were handed off downstream to integration, then manufacturing, then evaluated by chip and system designers, with feedback looping back slowly. This sequential approach worked when progress relied on relatively modular steps that could be scaled independently and dropped into the manufacturing flow. However, AI timelines have shattered these rules. At angstrom-scale dimensions, physics enforces inescapable coupling across the entire stack—materials choices in one layer affect performance in another. The traditional model is too slow and cannot handle the boundary-driven complexity. We need a new model that compresses feedback loops, fosters concurrent engineering across all domains, and enables rapid iteration on system-level solutions.

What is boundary-driven complexity in advanced chipmaking?

Boundary-driven complexity refers to the challenges that emerge at the interfaces between different domains of chip design and fabrication. In the angstrom era, the most difficult problems are no longer within a single domain (like making a faster transistor) but at the boundaries—between compute and memory in the package, between front-end (transistor) and back-end (interconnect) integration, and between the many tightly coupled process steps required for precise 3D fabrication. For example, optimizing memory proximity directly impacts thermal management and mechanical stress. These boundary conditions cannot be resolved by improving one domain in isolation; they require simultaneous, co-optimized solutions. This complexity is why traditional siloed innovation breaks down, and why a new integrated approach is essential for progressing AI chip performance.